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Designing High-speed Analog Signal Chains from DC-to-Wideband

Introduction

All the trend these days in the converter world may be the GSPS ADC- otherwise known as an RF ADC. With your high sample rate converters available on the market this opens up the Nyquist by 10× when compared to 5 years ago. A lot has been discussed concerning the benefits of using RF ADCs and the way to design together and capture data at such high rates. Thank you JESD204x consortium. But one consideration seems to be forgotten about, the lowly dc signal.

The design of the input configuration, or front end, ahead of a higher performance, analog-to-digital converter (ADC) is definitely important to achieving the desired system performance. Often the focus is capturing wideband frequencies, such as those greater than 1 GHz. However, in certain applications, dc or near dc signals are also required and can be appreciated towards the end user, as they too carry important information. Therefore, optimizing the overall front-end design to capture both dc and wideband signals needs a dc-coupled front-end that leads all of the way down to the high speed converter.

Because of the nature from the application, an energetic front-end design will have to be developed, as passive front ends and baluns used to couple the signals into the converter are inherently ac-coupled. In the following paragraphs an overview on the importance of common-mode signals and how to properly level shift the amplifier front-end will be provided in a real system solution example.

Common Mode: Overview

Many customer technical support questions still come in from customers when there is deficiencies in understanding of the common-mode parameter and how it requires the devices. ADC data sheets specify a common-mode voltage requirement of the analog inputs. Not much detailed information can be obtained on this subject, however the proper front-end bias must be maintained in order to achieve rated ADC's performance at full scale.

ADCs with integrated buffers typically have an internally biased commonmode (CM) level of half the availability along with a diode drop (AVDD/2 + 0.7 V). No external circuitry is needed to bias this circuit, however it should be maintained to properly make use of the converter. For unbuffered (switched capacitor input) converters, the common-mode bias is typically half the analog supply, or AVDD/2. This is often supplied externally in a number of ways.

Some converters possess a dedicated pin that allows the designer to supply bias via a handful of resistors associated with the analog inputs. Alternatively, the designer can connect the internal bias to some transformer's center tap or can make use of a resistor divider off the analog supply (a resistor from both legs of the analog inputs to AVDD and ground). Look into the manufacturer's data sheet or applications support group before while using converter's VREF pin, as many references are not equipped to supply a common-mode bias with no external buffer. It is tempting since the CM voltage you'll need is immediately and handy, but be warned-don't do it.

If the common-mode bias isn't provided or maintained, the converter will have gain and offset errors that contribute to the overall measurement. The converter may clip early, or not whatsoever, because the converter's full scale cannot be reached. Common-mode bias is especially important when connecting an amplifier while watching converter, especially if the application requires dc coupling. Look into the amplifier's data sheet specifications to make sure the amplifier can meet the converter's swing and common-mode supply requirements.

Converters have been pushing to smaller geometry processes and, therefore, lower supplies. Having a 1.8 V supply, a 0.9 V common-mode voltage is needed by the amplifier if dc coupling is needed. Amplifiers with 3.3 V to five V supply voltages may not be able to keep that low of the level, but newer low voltage amplifiers can, or the designer may use a split supply and use an adverse rail on the VSS pins. However, when you are performing this, keep in mind other pins also may have to be connected to the negative rail. Consult the data sheet and/or the direct application support for that product to discover.

Common Mode: Defined

Let's begin with defining exactly what a CM voltage is. Figure 1 shows the way a converter sees differential and common-mode signals. A CM voltage is just the center point around which the signals move-see Figure 1. You may also consider this because the new centerpiece or zero code-an amplifier, CM is established around the outputs, usually via a VOCM pin or similar. Be careful though, these pins have certain current and voltage range requirements too. It might be best to review the amplifier data sheet and/or make use of a robust bias point that doesn't load down any adjacent circuitry or reference point within your circuit. Don't simply tap off a converter's voltage reference pin (VREF), which is usually half the converter's full scale. It may not be able to provide enough bias with good accuracy. It might be prudent to examine the pin specifications on the converter's data sheet too. Usually something similar to an easy voltage divider with 1% resistor tolerances and/or a buffer driver works to create this CM bias = properly to have an amplifier.

In Table 1, a fast review of how to connect the amplifier and converter per application is listed below, in addition to some proper circuit examples shown in Figure 2.

Table 1. Common-Mode Matrix

Application Amplifier ADC Notes
DC-Coupled Set VOCM within limits specified on DS. Use voltage divider or buffer amp from ADC VREF/CML pin. Does not provide CM bias. Make sure both the amplifier and ADC CM bias are within range of one another.

Otherwise, a mismatch may cause errors.

AC-Coupled (with Unbuffered ADC) Set VOCM within limits specified on

DS. Use voltage divider as well as other stable bias point.

Sets VIN CM bias to AVDD/2.

Use voltage divider or CML pin to provide CM bias.

Place ac coupling caps on output of amplifier.
AC-Coupled (with Buffered ADC) Set VOCM within limits specified on

DS. Use voltage divider or some other stable bias point.

Does not provide CM bias. VIN pins are self biased to AVDD/2 + 0.7. Place ac coupling caps on creation of amplifier.

 

Common Mode: Broken

If the common-mode bias isn't provided or maintained, then the converter may have gain and offset errors that degrade towards the overall measurement being acquired. Simply put-the converter output will look like Figure 3 or some variation from it. The output spectrum will require around the form of appearing like an overloaded full-scale input. This means the zero reason for the converter is off center and not optimum. The designer could find the converter will clip early or not reach the full scale of the converter. Recently this problem has gotten worse since converters are using 1.8 V supplies minimizing.

This means the CM bias for the analog input is 0.9 V or AVDD/2. Not all single-supply amplifiers supports this type of low commonmode voltage while keeping relatively good performance. However, newer and more effective amplifiers have accommodated this and therefore are out on the market today. Therefore, it would be prudent to review which amplifiers may be used inside your new design. Not only any old amplifier will work because the headroom can become very constrained and the internal transistors start to cave in. If a dual supply is used by having an amplifier, there should be sufficient headroom in most cases to have the correct CM bias. However an additional supply-a negative supply that maybe nonstandard, which means more parts and more money. Simple inverter circuits works to help with this.

Putting It All Together

Now that common mode and dc coupling is thought, we are able to start putting together an indication solution. For instance, the ADL5567, that is a dual differential amplifier with 20 dB of gain. It's 4.8 GHz of bandwidth and it is ideal for interfacing with GSPS ADCs, such as the AD9625 a 12-bit, 2.5 GSPS converter having a JESD204B 8-lane interface. Figure 4 shows the general block diagram from the setup.

In this configuration shown, the front-end interface is optimized for wideband sampling while preserving the dc signal content. Because the part is +5.5 V tolerant. The look used a split +3.3 V and -2 V AVDD supplies. This made the common-mode alignment simple between your creation of the amplifier and inputs from the ADC, both of which needs to be +0.525 V on both AIN+ and AIN-. Also, notice that a couple of the amplifier pin functions that were ground-enabled (Vss) with just a single power supply are actually instructed to the -2 V supply (new Vss).

The CM voltage outputs are fairly straightforward but the knowledge of the amplifier inputs' common-mode needs can be a bit tricky. There's two stuff that have to be done here for the interface. First, the input CM voltage needs to be configured for 0 V. Otherwise, driving the amplifier with offset will let the outputs rail to 1 side. This would make the performance issues observed in Figure 3 or worse-where poor ac performance would be seen in the amplifier and converter signal chain. To get this done, both sides from the amplifier's input must allow for current circulation to the ground, or 2 V within this dc-coupled case. Therefore, a 2.2 kOhm resistor was added to each amplifier input to kill this offset current.

Here is when that works: the creation of the amplifier is ~0.525 V and the input CM voltage towards the amplifier is 0 V. By having an internal feedback resistor of 500 Ohm and roughly a 50 Ohm input resistor, this appears like 550 Ohm; or in our case we assume a 50 Ohm source resistance in parallel with 100 Ohm, this provides us 33 Ohm. The extra 20 Ohm in series then sums to 53 Ohm. This is in series with the 500 Ohm internal feedback resistor or a grand total of 553 Ohm. Meaning a 0.525 V resistor divider of 500 Ohm and 53 Ohm is developed. Which in turn, develops a current of 900 μA, (or 0.525/553). To shunt this off to ground or even the new VSS or -2 V, a 2.2 kOhm resistor was added or -2 V/2.2 kOhm = 900 μA.

Second, the input is single ended and requires to become configured properly to carry best performance while maintaining a minimal even order distortion. Again, the effective 100 Ohm in parallel using the 50 Ohm source resistance yields a Thevenin equivalent to 33.33 Ohm, as previously indicated. This, in turn, is typically reflected on both the VIN nodes to balance input from the device since it is being driven single ended. However, in order to improve even order distortion, 20 Ohm around the VIN+ node was used to keep the distortion low across all wideband frequencies. This is accomplished by using a specific midfrequency, ~500 MHz-or see Figure 5 like a test case. This is often tedious, because it is an iterative process. For calculations and equations in understand SE to DIFF conversion's on amplifiers, see the ADA4932 data sheet. Typical ac performance sweeps over input frequencies of up to 2 GHz is shown for that signal chain design in Figure 6.

It is also worth noting adding the five.1 nH inductor in series with the power supplies' positive rail input. This helps again to increase the even order linearity performance over frequency by capturing and recirculating these imbalanced currents internally in the amplifier.

Finally, the interface must be optimized for front-end BW between the amplifier and ADC. This is typically done in an iterative fashion as well. However, there are many notes to keep in mind on which sets certain values between the two ICs. The list below of rules can be applied to get the very best BW from the interface.

  • First, pick a kickback resistor (RKB), (Ohm in this case), according to experience and/or the ADC data sheet recommendations, typically between 5 Ohm and 36 Ohm.
  • Then, choose the amplifier external series resistor (RA). Make RA <10 Ohm when the amplifier differential output impedance is 100 Ohm to 200 Ohm. Make RA between 5 Ohm and 36 Ohm when the output impedance from the amplifier is 12 Ohm or less. In this instance, a 10 Ohm series resistance was chosen having a differential output impedance of 10 Ohm for the ADL5567.
  • The total mixture of resistors in series and parallel as seen through the amplifier's outputs should be close to the characterized load (RL) from the amplifier. In this instance, 160 Ohm, or 2 RA + 2 RKB + RADC = 20 + 40 + 100, in the circuit of Figure 4. The ADL5567 was characterized with an RL of 200 Ohm so expect some deviations in linearity performance if your design moves too far from the characterized RL of the amplifier.
  • Lastly, the interior ADC capacitance, CADC, increases the shunt C shown following the 10 Ohm series resistance to help with kickback from the internal ADC's sampling network. This also offers soft low-pass filtering to decrease any wideband harmonics that fold back in-band.

For a far more complete process in developing antialiasing filters between amplifiers and ADCs, see CN-0227 and CN-0238.

Using the factors over a 2 GHz pass-band flatness response was developed in order to capture frequencies inside the 1st and 2nd Nyquist zone, assuming 2.5 GSPS sampling. The input drive specification with this design winds up being -8 dBm or 252 mV p-p assuming a 50 Ohm input impedance at 100 MHz reference. This is the input full-scale level where the amplifier's input requires for that converter to achieve full scale.

Conclusion

Overlooking a converter's common-mode input voltage specification may cause havoc in any dc-coupled design. If multiple stages are utilized, the common-mode levels must be kept the same through the signal chain to avoid the 2 components from fighting each other. One will usually win between any stage if not coupled correctly, producing bogus measurements.

For ac-coupled applications, use a coupling capacitor between your two stages to interrupt the common-mode mismatches. This allows the design to optimize the bias of both amplifier output and the ADC input, for example.

Otherwise, dual supplies or level shifting circuits will need to be active in the system design, as described above within the dc-coupled design.

About the Author

Rob Reeder is a system application engineer with Analog Devices in the Aerospace and Defense Group in Greensboro, N.C., concentrating on military and aerospace applications. He's published numerous articles on converter interfaces, converter testing, and analog signal chain design for various applications. Formerly, Rob was an applications engineer for the high speed converter products for eight years. His prior experience includes test development and analog design engineer for that Multichip Products Group at ADI, designing analog signal chain modules for space, military, and reliability applications for 5 years.