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How you can Configure the Tracking and Power Sequencing of FPGAs


The increase of voltage input rails for delivering point-of-load power to DSPs, ASICs, FPGAs and microprocessors is creating more challenges for power supply designers. Especially as system power and operating frequency demands keep growing, causing infrastructure, industrial and factory automation equipment to become more responsive to noises and many unforeseeable events. For instance, false inputs at launch can trigger system latch up, reliability issues, as well as system failure.

This article discusses how to configure various voltage output tracking and sequencing choices for an FPGA or microprocessor that will the proper launch and shut down of sensitive multi-rail systems. We'll also check out a ratiometric and coincidental setting that prevents an FPGA's internal electrostatic discharge (ESD) diodes from biasing or being overstressed during rising or falling outputs. These configurations will improve system reliability, that is fundamental to the productivity and uptime of infrastructure systems and factory floor industrial equipment.

System Configuration

A typical application circuit configuration for an FPGA is shown in Figure 1. From the highest input rail of three.3V towards the second input rail of 2.5V, we find back-to-back ESD diodes serving as internal protection circuits. Then another group of back-to-back ESD diodes is configured from the second input rail towards the third rail.

Let's assume a case where the highest input rail, which is the 3.3V within this example, begins first before every other rails. It then pre-biases the 2.5V output rails to approximately 1.9V and the 1.8V rail to at least one.2V. Similarly, the 1.8V rail pre-biases the 2.5V and also the 3.3V rail if it come up first. In either case, the ESD diodes must conduct during launch. Figure 2 illustrates the voltage signals of the input rails for 3.3V and also the signal it will send towards the 2.5V prior to it being active. The charging current with the ESD diodes depends upon the start-up slew rate, the 2.5V output capacitances, and then any loading. Running exactly the same start up scenario using the 1.8V output rail will exhibit similar voltage signals.

Each time the ESD diodes conduct, their reliability is degraded. Figure 3 illustrates what goes on towards the 3.3V and 2.5V rails when the 2.5V input source is not rated for pre-biased launch. As you can tell, the FPGA's internal ESD diodes are stressed when the 2.5V rail starts up. Therefore, using a source of energy that's rated with pre-biased start up avoids this issue and averts the potential for system latch up. Step-down regulators with correctly configured output power tracking will ensure that all of the system rails properly soft-start together and prevent the ESD diodes from conducting. This simple step will improve system reliability and steer clear of any unforeseen system power latching.

Integrated FET DC/DC Converters

Presented in Figure 4 is a typical application circuit for any 2A DC/DC converter having a 2.7V to five.5V input voltage range. Just a few external components, including resistors, capacitors and inductor are required. The converter integrates the compensation and also the power MOSFETs to guarantee design robustness, minimum part counts, and efficiency up to 95%.

The converter's Pin 5 provides both soft-start (SS) and output tracking (TR) functions. If this pin is connected high, the soft-start time is internally set to 1ms. However, various soft-start schemes can be achieved using external components. Figure 5 illustrates the way the SS/TR feature can be used to program external soft-start time.

Simply set the soft-start resistor RSS and capacitor CSS to regulate the time. The approximate relationship is shown in Equation 1:

Equation 1.

This soft-start feature may also be configured for tracking other outputs. Figure 6 shows a ratiometric tracking configuration of VOUT1 to VOUT2.

In addition, you are able to connect the two SS/TR together to make the 2 output voltages to increase at the same time. Similarly, the shutdown function also tracks each other ratiometrically, as with the soft-start time described in Equation 1.

Coincidental tracking could be configured as shown in Figure 7. Simply add a resistive divider that is the same ratio as its output voltage sense divider in the feedback loop. In this instance, all the output voltages increase with similar voltage and slew rate according to the main rail. Typically, the greatest rail is what other outputs should track to. Then each output will branch out as they reach their regulation point. With all of the output rails launch and shut down inside a well-controlled fashion, you'll avoid the Figure 1 internal ESD diodes from conducting or from being forward biased. Most significantly, this design technique prevents any degradation in system reliability, latch up conditions, or worse – system failures in the field.


Integrated FET step-down regulators, such as the ISL8002B, offer numerous simple to apply solutions for tracking voltages during power up and turn off sequencing. Nearly any system voltage tracking requirement could be configured and among the block circuits discussed in the following paragraphs. These configurations aren't restricted to two regulators, as they possibly can be applied to any number of rails within your system. Simply connect all of the SS/TR pins together for ratiometric tracking. Alternately, use a resistive divider to program the machine for coincidental tracking. Either the ratiometric or coincidental tracking method will prevent unnecessary stress over the ESD diodes to improve your system's overall reliability.

Courtesy: www.renesas.com