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Multichannel Clocking Reference Design for DSO, Radar, and 5G Wireless Testers

Description

The TIDA-01021 design is capable of supporting two high-speed channels on separate boards by using TI’s LMX2594 wideband PLL with integrated VCOs to manufacture a 10-MHz to 15-GHz clock and SYSREF for JESD204B interfaces. The 10-kHz offset phase noise is < -104 dBc/Hz for your 15-GHz clock frequency. This TI Design uses TI’s ADC12DJ3200 high-speed converter EVMs to achieve a board-to-board clock skew of < 10 ps with an SNR of 49.6 dB using a 5.25- GHz input signal. All key design theories are described, guiding users throughout the part process and design optimization. Finally, this reference design presents schematics, board layout, hardware testing, and results.

 

Features

  • Up to 15-GHz Sample Clock Generation
  • Multichannel JESD204B Compliant Clock Solution
  • Low-Phase Noise Clocking for RF Sampling ADC and DAC
  • Configurable Phase Synchronization to quickly attain Low Skew in Multichannel System
  • Supports TI’s High-Speed Converter and Capture Cards (ADC12DJ3200EVM, TSW14J56, and TSW14J57)

Applications

  • High-Performance Oscilloscopes
  • Phased Array Radars
  • Wireless Communication Testers
  • Direct Sampling Software Defined Radio

1? System Description?

Clocking solutions for high-speed GSPS direct RF sampling signal chains are essential to achieve high SNR and low channel-to-channel skew. This reference design demonstrates a multichannel phase synchronized clocking platform which you can use in applications like DSO, phased array radars, and 5G wireless testers. While using the LMX2594 frequency synthesizer for DEVCLK and SYSREF generation, this TI Design can clock JESD204B data converters. Furthermore, using the LMK04828 to obtain the FPGA clocks and SYSREF signals, multiple channels is usually supported.

In this solution, two LMX2594 devices obtain a 100-MHz VCXO reference signal with the LMK04828 and generate phase synchronized DEVCLK (sampling clock) and SYSREF for two main high-speed signal chains. The LMK04828 clock jitter cleaner generates independent SYSREFREQ signal and SYNC signal to both LMX2594 devices for SYSREF generation. The LMK04828 generates FPGA device clocks per channel that happen to be synchronized into the respective SYSREFREQ outputs.

High-performance multichannel digital storage oscilloscopes call for a signal chain that has a wideband analog front, high SNR, and low channel-to-channel skew. The ADC12DJ3200 ADC is appropriate for these requirements. The clocking solution described in such a TI Design provides an optimum solution for clocking the ADC12DJ3200 ADCs to achieve high SNR and low channel-to-channel skew.

Wireless tester equipment use multichannel receivers for testing cellular and MIMO devices. Wireless testers require high dynamic range and wideband receivers to check 3G and later on wireless standards-compliant equipment. The ADC12DJ3200 is appropriate for the multichannel receiver requirements of the wireless testers. The clocking solution described during this TI Design supplements a high-performance signal chain solution depending on multiple ADC12DJ3200 ADCs to accomplish the minimum time skew between channels providing both high dynamic range and wide receiver.

Phased array radar applications need to have a high dynamic range, wide receiver bandwidth, low latency, and good synchronization regarding the channels. The signal chain solution depending on the LMX2594, ADC12DJ3200, and LMK04828 appliances are competent to achieve optimum performance for phased array radar applications.

Direct RF-sampling software-defined radio (SDR) technology needs multiple channels, high dynamic range, highly re-configurable receiver bandwidth, and wide input frequency range. This TI Design can meet the criteria on the high-performance SDRs concerning multichannel, dynamic range, and reconfigurability.

1.1? Key System Specifications?

The objective of the TI Design is to demonstrate a high-speed clocking solution for any multichannel signal chain. Phase noise and jitter performance with the LMX2594 with an onboard crystal or LMK61E2 reference is shown in Table 1. The TIDA-01021 design targets measuring the SNR at the

ADC12DJ3200 signal chain and configurable phase delay to align multichannel clocks. The details capture is done with the TSW14J56, that’s interfaced when using the ADC12DJ3200EVM using an FMC adapter card.

Table 1 lists the main element system level specifications for any signal chain with the clocking solution perspective.

Table 1.? Key System Specifications

PARAMETER SPECIFICATIONS CONDITIONS
Dev_Clk phase noise -117.0 dBc/Hz at 10-kHz offset

-119.7 dBc/Hz at 100-kHz offset

-130.5 dBc/Hz at 1-MHz offset

-149.5 dBc/Hz at 10-MHz offset

at 3.5 GHz
-108.8 dBc/Hz at 10-kHz offset

-111.4 dBc/Hz at 100-kHz offset

-123.1 dBc/Hz at 1-MHz offset

-147.4 dBc/Hz at 10-MHz offset

at 9 GHz
-104.7 dBc/Hz at 10-kHz offset  
  -107.5 dBc/Hz at 100-kHz offset

-114.7 dBc/Hz at 1-MHz offset

-141.7 dBc/Hz at 10-MHz offset

at 15 GHz
SNR (dBFS) (dual channel mode) 56.3 at a 997-MHz ADC input signal
55.2 at a 2482-MHz ADC input signal
52.6 at a 5250-MHz ADC input signal
Multichannel clock time skew < 10 ps at a 3-GHz clock output
Channel-to-channel time skew < 50 ps at a 997-MHz ADC input signal
at a 2482-MHz ADC input signal

?

Overview

2? System Overview

2.1? Block Diagram

Figure 1 shows the block diagram on the high-speed multichannel clock solution interface when using the ADC12DJ3200 EVM and TSW14J56 capture cards. The ADC12DJ3200 EVM is interfaced when using the TSW14J56 data capture board by using an FMC+ adapter board. The ADC DCLK and SYSREF are given on the TIDA-01021 clocking board while using the length matched cables.

System Overview

2.2?????? Highlighted Products

2.2.1???????? LMX2594

The LMX2594 is usually a high-performance, wideband RF PLL with integrated VCO that supports a frequency are priced between 10 MHz to fifteen GHz without having to use an internal doubler. These devices supports both fractional-N and integer-N modes, having a 32-bit fractional divider allowing fine frequency selection. The high-performance PLL by using a figure of merit of -236 dBc/Hz as well as phase detector frequency can attain really low in-band noise and integrated jitter. Its integrated noise of 45 fs for a 7.5-GHz output is the device an excellent low-noise source.

The device accepts a port reference frequency about 1.4 GHz, which mixes with frequency dividers and programmable low-noise multiplier to enable flexible frequency planning. The high-speed N-divider lacks the pre-divider, thus significantly reducing the amplitude and amount of spurs. Any additional programmable low-noise multiplier allows users to mitigate the impact of integer boundary spurs. In fractional-N mode, the product can adjust the output phase by way of a 32- bit resolution.

For applications that requirement fast frequency changes, the unit supports a rapid calibration option, which will take fewer than 20