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Understanding Electromigration and IR Stop by Semiconductor Chip Design: Challenges and Techniques

Abstract

As we push through lower technology nodes within the IC and chip design, the wire width goes thinner together with transistor size. This will make the wire resistance more dominant on 16nm and below technology nodes. This increasing resistance and the decreasing width of metal wires introduce many Electromigration and IR drop issues. Both of these issues play major roles in reducing the lifespan of the digital camera and are what causes functionality failure in any electronics with lower technology nodes.

In this short article, we will discuss the issues of electromigration and IR drop, and methods to prevent the appearance of these problems in electronics.

Technology Trends Impacting Nanometer Sizes:

The technology trends and demand for compact electronic devices require modern IC designs. Electronics manufacturers are exponentially decreasing the metal interconnect width. Consequently, the cross-sectional area of interconnect is shrinking. Moreover, due to the increasing functionality integration and devices interconnection, there are more wires on a die. Hence, any device working on nodes lesser than 16nm is susceptible to performance issues over a period, because of the failure of passing proportionate currents, resulting in problems with electromigration and IR drop.

What is Electromigration?

Electromigration (EM) is a molecular displacement due to the momentum transfer between conducting electrons and ions during a period of time. It happens once the density of the present is high, which in turn causes the metal ions to drift in direction of electron flow. EM usually occurs after years of deployment of devices within the field.

Due to electromigration effects, the metal wires may burst into open and shorts. EM can increase wire resistance, which can cause a voltage drop leading to device slowdown. It can also cause permanent failure in circuits because of shorts or opens. EM goes in a positive feedback loop with temperature (Joule Heating). Here is how to find the Mean Time for you to Failure (MTTF) of the metal line with Black's Equation.

Electromigration reliability of a wire (Black’s equation)

A = Cross-section area dependent constant

Jn = Current density

Ea = Activation energy k = Boltzmann’s constant T = Temperature in kelvins

N = Scaling factor (usually set to two based on Black)

What is IR Drop?

IR drop is the voltage stop by the metal wires constituting the ability grid before it reaches the ability pins from the standard cells. It becomes very important to limit the IR drop as it affects the speed from the cells and efficiency from the chip. There's two types of IR drops:

  1. Static
  2. Dynamic

Static IR Drop:

Static IR drop is an average voltage drop for the design. It's dependent on the RC of the power grid connecting the power supply towards the respective standard cells. The typical current depends totally on the time period. Gate-channel leakage current is the major reason for the static IR drop.

Vstatic_drop = Iavg x Rwire [Iavg are all factors of leakage currents ]

Dynamic IR Drop:

Dynamic IR drop is really a stop by the voltage due to the high switching activity of transistors. It happens when there is an increasing interest in current in the power because of switching activities from the chip. Dynamic IR drop depends upon the switching time of the logic and is less dependent on the time period. Dynamic IR drop evaluates the IR drop caused whenever a many circuitry switches at the same time, causing peak current demand. This current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps), and may lead to an IR drop that causes additional setup or hold-time violations. Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path signal nets causes setup-time violations. In such instances, you are able to separate the standard cells apart so the burden on a given bump to feed many standard cells, that have high switching activity, can be mitigated.

Vdynamic_drop = L (di/dt) [current L is a result of switching current]

A Case in Point:

EM violations in networking ASIC in 16nm FF+

We observed 1155 electromigration violations on signal/clock nets. We had max_cap of 371fF load and average net length was ~640um. Capacitance load took it's origin from the default value in the standard cell lib. This enabled nets to allow more current.

Total capacitance of APSDRC_net_210033: 0.34327 Total length of APSDRC_net_210033: 1345.995

IR challenges in networking ASIC in 16nm FF+

We saw an IR drop around clock cells ever since they were always switching having a duty cycle of 50%. We observed that there were standard cells in close proximity of clock cells through which the general area got very denser. Due to this, there was an IR drop around such areas.

Apart from the clock, we had an IR drop hotspot on a few of the power-hungry cells and highly dense region.

Techniques to avoid Electromigration and IR Drop

Electromigration Mitigation

  1. Apply NDR (Non-default Rule) on the violated nets (vulnerable nets)

Once you will find the EM results, you are able to take the net shapes and re-route those nets using the NDR. Applying NDR involves routing of clock nets using double-wide or triple-wide metal with increased spacing. This can quickly remove most of the violations and can even predict the nets, for likely to have EM violation based on two parameters: 1) driver strength and a pair of) load.

You can remove nets with increased load and high drivers and move them to NDR. You are able to decide the threshold load for various driving strength according to project statistics.

Example: We had an incredible improvement on one of the blocks

Command: create_routing_rule em_ndr -widths “M2 0.064 M3 0.064 M4 0.064” -cuts VIA1 Vrh 1 Vrv

1 VIA2 Vrh 1 Vrv 1 VIA3 Vrh 1 Vrv 1 VIA4 Vr 1

foreach net [gon [get_nets $nets] ] set_routing_rule $net -rule em_ndr

Before these settings, there have been 309 violations, which reduced to at least one after applying NDRs.

2. Restricting load target for nets

Restricting or reducing the strain on the nets can also be useful in preventing the appearance of electromigration. In the above example, we had 142fF as an average capacitance within the design. In line with the statistics of a few experiments, we restricted all nets to possess a maximum 60fF of load. Consequently, we saw an excellent improvement in signal EM and also on average net length.

Command: set_max_capacitance 0.06 [current_design] #setting max_cap_value for that design

IR Drop Mitigation

  1. Padding clock cells

When it comes to IR drop issues, clock structure is the primary culprit for that power consumption of the chip because of high clock switching. However, with padding clock cells technique, clock buffers/inverters and clock gate cells are given extra area as keepout regions to avoid placement of standard cells and any excessive cell density around them. This helps to prevent the dynamic IR drop.

Command: create_keepout_margin -outer 3.6 0.576 3.6 0.576 $clock_type_keepout IMAGE: A cell with cell padding

2. Cell Padding/Decap insertion around cells inside a dynamic IR hotspot region

Some cells rich in driving strength create dynamic IR drop issue. You are able to give cell padding to these cells or insert decap cells around it or IR hotspot region to prevent IR drop issues.

Conclusion:

When you are looking at lower geometry designs, the problems of IR drop and electromigration are typical. In manners like padding on clock cells, restricting maximum strain on nets and applying NDR on clock nets, you are able to prevent major IR drop issues and reduce electromigration in lower geometry chip designs.